	// verilator_coverage annotation
	module stage_wb(
 000272	    input  wire[31:0]  wb_mem_data,
 000659	    input  wire[31:0]  wb_alu_o,
 000013	    input  wire        wb_mem2reg,
 000486	    output wire[31:0]  w_regs_data,
%000423	    input wire[31:0] wb_matrix_mopa_o[3:0],
%000414	    output wire[31:0] w_matrix_mopa[3:0]
	);
	
	assign w_regs_data = wb_mem2reg ? wb_mem_data : wb_alu_o;
	assign w_matrix_mopa[0] = wb_matrix_mopa_o[0];
	assign w_matrix_mopa[1] = wb_matrix_mopa_o[1];
	assign w_matrix_mopa[2] = wb_matrix_mopa_o[2];
	assign w_matrix_mopa[3] = wb_matrix_mopa_o[3];
	
	endmodule
	
